 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| B9947 3.3V, 160-MHz, 1:9 Clock Distribution Buffer Product Features * * * * * * * * * 160-MHz Clock Support LVCMOS/LVTTL Compatible Inputs 9 Clock Outputs: Drive up to 18 Clock Lines Synchronous Output Enable Output Three-state Control 350-ps Maximum Output-to-Output Skew Pin Compatible with MPC947 Industrial Temp. Range: -40C to +85C 32-Pin TQFP Package Description The B9947 is a low-voltage clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible clock inputs. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The nine outputs are 3.3V LVCMOS or LVTTL compatible and can drive two series terminated 50 transmission lines. With this capability the B9947 has an effective fanout of 1:18. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the B9947 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The B9947 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram Pin Configuration VSS VDDC Q0 VSS Q1 VDDC Q2 VSS VDD TCLK0 TCLK1 TCLK_SEL SYNC_OE TS# 0 1 VDDC 9 Q0-Q8 32 31 30 29 28 27 26 25 VSS TCLK_SEL TCLK0 TCLK1 SYNC_OE TS# VDD VSS 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 B9947 9 10 11 12 13 14 15 16 VSS Q3 VDDC Q4 VSS Q5 VDDC VSS Cypress Semiconductor Corporation Document #: 38-07078 Rev. *C * 3901 North First Street * San Jose * VSS VDDC Q8 VSS Q7 VDDC Q6 VSS CA 95134 * 408-943-2600 Revised December 22, 2002 B9947 Pin Description Pin 3 4 2 11, 13, 15, 19, 21, 23, 26, 28, 30 5 Name TCLK0 TCLK1 TCLK_SEL Q(8:0) SYNC_OE VDDC PWR I/O I, PU I, PU I, PU O I, PU Test Clock Input Test Clock Input Test Clock Select Input. When LOW, TCLK0 is selected. When asserted HIGH, TCLK1 is selected. Clock Outputs Output Enable Input. When asserted HIGH, the outputs are enabled and when set LOW the outputs are disabled in a LOW state. Three-state Control Input. When asserted LOW, the output buffers are three-stated. When set HIGH, the output buffers are enabled. 3.3V Power Supply for Output Clock Buffers 3.3V Power Supply Common Ground Description 6 TS# I, PU 10, 14, 18, 22, 27, 31 7 1, 8, 9, 12, 16, 17, 20, 24, 25, 29, 32 Note: 1. PU = Internal Pull-Up. VDDC VDD VSS Output Enable/Disable The B9947 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1. TCLK SYNC_OE Q Figure 1. SYNC_OE Timing Diagram Document #: 38-07078 Rev. *C Page 2 of 5 B9947 Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............ VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................-65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum ESD protection .............................................. 2 KV Maximum Power Supply: ................................................5.5V Maximum Input Current:..................................................20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters: VDDC = 3.3V 10%, VDD = 3.3V 10%, TA = -40C to +85C Parameter Description Input Low Voltage Input High Voltage IIL IIH VOL VOH IDD Cin Input Low Current (@VIL = VSS) Note 3 Input High Current (@VIL =VDD) Output Low Voltage Output High Voltage Quiescent Supply Current Input Capacitance IOL = 20 mA, Note 4 IOH = -20 mA, VDDC = 3.3V, Note 4 All VDDC and VDD 2.5 1 2 4 Conditions Min. VSS 2.0 Typ. Max. 0.8 VDD -100 10 0.4 Unit V V A A V V mA pF AC Parameters[5]: VDDC = 3.3V 10%, VDD = 3.3V 10%, TA = -40C to +85C Parameter Fmax Tpd FoutDC tpZL, tpZH tpLZ, tpHZ Tskew Tskew (pp) Ts Th Tr/Tf Description Maximum Input Frequency[6] TCLK to Q Delay[6] Output Duty Cycle[6,7] Output Enable Time (all outputs) Output Disable Time (all outputs) Output-to-Output Skew[6,9] Part to Part Skew[10] Set-up Time[6,8] Hold Time[6,8] Output Clocks Rise/Fall Time[9] SYNC_OE to TCLK TCLK to SYNC_OE 0.8V to 2.0V 0.0 1.0 0.20 1.0 Conditions Min. 160 4.75 Measured at VDDC/2 TCYCLE/2 - 800 2 2 9.25 TCYCLE/2 + 800 10 10 350 2.0 Typ. Max. Unit MHz ns ps ns ns ps ns ps ps ns Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up resistors that effect input current. 4. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Outputs driving 50 transmission lines. 7. 50% input duty cycle. 8. Set-up and Hold times are relative to the falling edge of the input clock 9. Outputs loaded with 30pF each 10. Part to Part Skew at a given temperature and voltage Document #: 38-07078 Rev. *C Page 3 of 5 B9947 Package Drawing and Dimensions 32-Pin TQFP Outline Dimensions Inches Symbol D Millimeters Max. 0.047 0.006 0.041 0.018 Min. 0.05 0.95 0.30 Nom. 9.00 7.00 0.80 BSC 0.030 0.45 0.75 Max. 1.20 0.15 1.05 0.45 Min. 0.002 0.037 0.012 Nom. 0.354 0.276 0.031 BSC A A1 A2 D D1 12 A1 D1 b e L 0.018 - L e b Ordering Information Part Number[11] B9947CA Package Type 32-Pin TQFP Production Flow Industrial, -40C to +85C Note: 11. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress B9947CA Date Code, Lot # B9947CA Package A = TQFP Revision Device Number Document #: 38-07078 Rev. *C Page 4 of 5 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. B9947 Document Title: B9947 3.3V, 160-MHz, 1:9 Clock Distribution Buffer Document Number: 38-07078 REV. ** *A *B *C ECN NO. 107114 108058 109804 122763 Issue Date 06/06/01 07/03/01 01/31/02 12/22/02 Orig. of Change IKA NDP DSG RBI Description of Change Convert from IMI to Cypress Changed Commercial to Industrial (See page 6) Convert from Word to Frame Add power up requirements to maximum ratings information Document #: 38-07078 Rev. *C Page 5 of 5 |
Price & Availability of B9947
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |